1. Field of the Invention
The present invention relates to a method for manufacturing a liquid crystal display (LCD) device, and more particularly, to a structure and method for manufacturing an LCD device to prevent a disconnection of a data line.
2. Discussion of the Related Art
As the information society develops demands for various types of display devices increase. Accordingly, many efforts have been made to research and develop various flat display devices, such as liquid crystal displays (LCD), plasma display panels (PDP), electroluminescent displays (ELD), and vacuum fluorescent displays (VFD), and some species of the flat display devices are already applied to displays of various types of equipment. Among the species of flat display devices, the liquid crystal display (LCD) device has been most widely used due to advantageous characteristics, such as thin profile lightweight and low power consumption, as a substitute for the Cathode Ray Tube (CRT). In addition to the mobile type LCD devices, such as a display for a notebook computer, LCD devices have been developed for computer monitors and televisions to display broadcasting signals.
Despite various technical developments in the LCD technology for applications in different fields, research for enhancing the picture quality of the LCD device has been in some respects lacking as compared to other features of the LCD device. To use the LCD device in various fields as a general display, the key lies in whether the LCD device can implement a high quality picture with high resolution and high luminance in a large-sized screen while still maintaining light weight, thin profile and low power consumption.
The LCD device includes an LCD panel for displaying an image and a driving part for applying a driving signal to the LCD panel. The LCD panel includes first and second glass substrates bonded to each other with a gap therebetween, and a liquid crystal layer injected between the first and second glass substrates. On the first glass substrate, otherwise known as a TFT substrate, there are a plurality of gate lines arranged in a first direction at fixed intervals, a plurality of data lines arranged in a second direction perpendicular to the gate lines at fixed intervals, a plurality of pixel electrodes in respective pixel regions defined by the gate and the data lines in a matrix and a plurality of thin film transistors (TFTs) switchable in response to a signal on the gate line for transmission of a signal on the data line to each pixel electrode. On the second glass substrate, otherwise known as a color filter substrate, there are a black matrix layer for preventing light leakage from regions except for the pixel regions, R/G/B color filter layers for displaying colors, and a common electrode for implementing an image. In case of an in-plane switching mode LCD device, the common electrode is formed on the first substrate.
The first and second glass substrates have a predetermined gap formed therebetween by spacers. The first and second glass substrates are bonded to each other by a sealant. The sealant has a liquid crystal injection inlet for injecting liquid crystal. While the space between the bonded first and second substrates is maintained in a vacuum state, the liquid crystal injection hole is positioned into a liquid crystal container such that the liquid crystal is injected between the first and second substrates by osmotic action. Then, when the liquid crystal is completely injected between the first and second substrates, the liquid crystal injection hole is sealed.
In the related art LCD device, an amorphous silicon (a-Si) thin film transistor (TFT) is generally used. However, TFTs formed of a polycrystalline silicon having a high mobility can be integrated into the LCD device such that polycrystalline silicon TFTs are substituted for amorphous silicon TFTs. In addition, the polycrystalline silicon TFTs can be formed as a complementary (CMOS) TFTs when used in driving circuits.
A polycrystalline silicon TFT is greatly affected by hot carrier stress (HCS) and high drain current stress (HDCS) since a polycrystalline silicon TFT has high electron mobility as compared with a amorphous silicon TFT. As channel length becomes shorter, the polycrystalline silicon TFT is more greatly affected by HCS and HDCS, thereby degrading reliability of the polycrystalline silicon TFT. The polycrystalline silicon TFT is manufactured at a temperature similar to that of the amorphous silicon TFT and then developed by crystallization technology using a laser such that polycrystalline silicon TFT is applied to a large-sized glass substrate.
The polycrystalline silicon TFTs can be used in the TFTs of the driving circuits and TFTs of the pixels that are both formed on a glass substrate. The polycrystalline silicon TFTs in the driving circuits can be switched at a high frequencies due to the high electron mobility characteristic of the polycrystalline silicon. However, the polycrystalline silicon TFTs for the pixels have a high drain current value during the switch-off state, thereby generating problems in operating polycrystalline silicon TFT as a switching device for a pixel. To decrease the current during the switch-off state in the polycrystalline silicon TFTs of the pixels, the polycrystalline silicon TFTs of the pixels are formed having a lightly doped drain (LDD) structure, an offset structure, and/or a dual gate structure.
FIG. 1 is a plan view illustrating a pixel of a related art LCD device. As shown in FIG. 1, a plurality of gate lines 11 are formed in one direction on a lower substrate 10 at fixed intervals and a plurality of data lines 12 are formed perpendicular to the gate lines 11, thereby forming a plurality of pixel regions P on the lower substrate 10. A pixel electrode 16 is formed in each pixel region P defined by the plurality of gate and data lines 11 and 12. A thin film transistor T is formed in each pixel region P. The thin film transistor T is switched according to a signal from the gate line 11 such that a signal of the data line 12 is transmitted to the pixel electrode 16.
The thin film transistor T includes a gate electrode 13 protruding from the gate line 11, a gate insulating layer (not shown) formed on the gate electrode 13 and an entire surface of the lower substrate 10, a semiconductor layer 14 on the gate insulating layer (not shown) above the gate electrode 13, a source electrode 15a protruding from the data line 12, and a drain electrode 15b facing the source electrode 15a. The drain electrode 15b is electrically connected to the pixel electrode 16 through a contact hole 17.
The lower substrate 10 having the aforementioned structure is bonded to an upper substrate (not shown) with a predetermined gap therebetween. The upper substrate includes a black matrix layer defining an opening corresponding to the pixel region P of the lower substrate 10 and for preventing light from leaking from regions except the pixel regions. Red R, Green G, or Blue B color filter layers are provided in the opening for displaying colors. A common electrode for driving a liquid crystal with the pixel electrode (reflecting electrode) 16 is provided on the color filter layers R, G and B. The predetermined gap between the upper and lower substrates is determined by spacers. The first and second glass substrates are bonded to each other by a sealant. The sealant has a liquid crystal injection inlet through which the liquid crystal is injected.
A method for manufacturing the related art LCD device will be explained in reference to FIGS. 2A and 2I. More particularly, FIG. 2A to FIG. 2I are cross-sectional views illustrating manufacturing process steps of the related art LCD device shown in FIG. 1. As shown in FIG. 2A, a buffer layer 22 of a silicon oxide material is formed on an insulating substrate (TFT array substrate) 21, and then an amorphous silicon layer is formed on the buffer layer 22. Subsequently, energy, such as laser, is applied to the amorphous silicon layer, thereby forming a polycrystalline silicon layer. The polycrystalline silicon layer is selectively removed by photolithography such that active layer (semiconductor layer) 23 is formed. Then, as shown in FIG. 2B, a metal layer having a low resistance is deposited on the gate insulating layer 24, and then selectively removed by photolithography, so that a plurality of gate lines 25 with protruding gate electrodes 26 are formed at fixed intervals in one direction. For example, the metal layer having the low resistance is formed by sputtering a conductive metal material, such as an aluminum alloy AlNd, chrome Cr, tungsten W, or molybdenum Mo.
As shown in FIG. 2C, n-type impurity ions or p-type impurity ions, depending on the conductivity type of the TFT, are selectively doped into the active layer 23 on the insulating substrate 21 by using the gate electrode 26 as a mask such that LDD regions 27 are formed in the active layer 23 on both sides of the gate electrode 26. Then, as shown in FIG. 2D, a photoresist layer 28 is deposited over the entire surface of the insulating substrate 21, and then selectively patterned by photolithography to be formed surrounding the gate electrode 26. Subsequently, highly doped p-type or n-type impurity ions are selectively doped into the active layer 23 in FIG. 2C by using the patterned photoresist layer 28 as a mask, thereby forming source and drain regions 29 in the active layer 23.
As shown in FIG. 2E, when using PH3+H2 for doping impurity ions to form the source and drain regions 29, the photoresist 28 changes characteristics in that a portion of it becomes harder. Accordingly, a CF4+O2 plasma process is needed to etch the hardened portion of the photoresist. However, during the plasma process for etching the hardened portion of the photoresist, a portion of the surface of the gate insulating layer 24 is removed from under the gate line 25. The rest of the photoresist layer 28 is completely removed by a subsequent stripping process. In other words, due to the CF4+O2 plasma process, a predetermined thickness A of the gate insulating layer 24 is removed.
Referring to FIG. 2F, an insulating interlayer 30 is formed over the entire surface of the insulating substrate 21 including the gate electrode 26. The insulating interlayer 30 and the gate insulating layer 24 are then selectively removed to expose upper surfaces of the source and drain regions 29, thereby forming first contact holes 31. As shown in FIG. 2G, a metal layer is deposited over the entire surface of the insulating substrate 21 including the first contact holes 31. Source and drain electrodes 32a and 32b are formed by etching the metal layer using photolithography. The source electrode 32a is also a data line.
As shown in FIG. 2H, a passivation layer 33 is formed over the entire surface of the insulating substrate 21 including the source and drain electrode 32a and 32b, and then selectively removed to expose a predetermined portion of the drain electrode 32b, thereby forming a second contact hole 34 in FIG. 2H.
Referring to FIG. 2I, a metal layer is then deposited over the entire surface of the insulating substrate 21 including the second contact hole 34, and then selectively patterned to form a pixel electrode 35 connected to the drain electrode 32b through the second contact hole 34. Although not shown, a color filter substrate having a color filter layer and a common electrode is formed facing the TFT array substrate. Then, the color filter substrate and the TFT array substrate are bonded to each other, and a liquid crystal is injected between the color filter substrate and the TFT array substrate.
FIG. 3 is a plan view illustrating a data line perpendicular to a gate line according to manufacturing process steps according to the related art. FIG. 4 is a cross-sectional view illustrating a related art LCD device taken along line II-II′ of FIG. 3. As shown in FIG. 3 and FIG. 4, the gate insulating layer 24 below the gate line 25 crossing under the data line 32 is overetched, as shown by “C” in FIG. 4, when removing the photoresist layer 28 shown in FIG. 2E. A disconnection, shown as a dotted line in FIG. 3, occurs due to a failure of step coverage in the insulating interlayer 30 when forming the data line 32.
The related art method for manufacturing the LCD device has disadvantages. For example, the gate insulating layer is partially etched at a predetermined portion adjacent to the gate line when removing the photoresist layer because of a change in the surface of the photoresist layer during the doping of impurity ions into the source and drain regions. In the case of forming CMOS transistors, a process of depositing and removing the photoresist layer is repetitively performed such that the depth of the gate insulating layer, which is etched, is further increased. Accordingly, if the insulating interlayer is deposited on the gate insulating layer when the gate insulating layer is overetched, the disconnection of the data line generates due to the insulating interlayer having poor step coverage.